Performance Study of a Multithreaded Superscalar Microprocessor

This paper describes a technique for improving the performance of a superscalar processor through mul-tithreading. The technique exploits the instruction-level parallelism available both inside each individual stream, and across streams. The former is exploited through out-of-order execution of instructions within a stream, and the latter through execution of instructions from diierent streams simultaneously. Aspects of multithreaded superscalar design, such as fetch policy, cache performance, instruction scheduling, and functional unit utilization are studied. We analyze performance based on the simulation of a superscalar architecture and show that it is possible to provide support for multiple streams with minimal extra hardware, yet achieving signiicant performance gain (20-55%) across a range of benchmarks.